Implementation of hardware security primitives with emerging non-volatile technologies
Classically, hardware security research uses mature technologies and well-established embedded devices to implement cryptographic algorithms or specific hardware primitives such as random number generators or physical unclonable functions. However, new applications-oriented domains such as the Internet of things but also high-level computing areas (including artificial intelligence for example) led to the need for new architectures which must be secure from the hardware. Indeed, these domains include an impressive quantity of data to be processed by computing architectures and emphasize the Von Neumann bottleneck. A solution to overcome this bottleneck is to use emerging non-volatile technologies such as resistive (RRAM), magnetic (MRAM) or ferroelectric technologies (FeRAM and FeFET). Despite the great interest of the system design community for the wide range of applications these technologies can address, hardware security challenges and opportunities still have to be covered. In this presentation, I will have particular attention for the ferroelectric field effect transistor. I will show how they can be used to implement part of cryptographic algorithms with high energy efficiency, why they can be interesting against classical side channel attacks and how it is possible to integrate them inside known computing architectures.
Cédric Marchand received an engineering degree in 2013 from the French “Ecole des Mine de Saint-Étienne” specialized in micro-electronics and applications. Then, he received his PhD in 2016 from University of Lyon for his research on the conception of salutary hardware to fight against counterfeiting and theft of integrated circuits. He received in 2017 a prize of excellence from the Foundation of the Jean Monnet university of Saint-Étienne for his thesis. In 2017, he integrated the heterogeneous system design team at École centrale de Lyon as associate professor. In 2021, he joined the GDR security and the GDR system on chip, embedded system and connected object (SOC2) as co-responsible for the working group on hardware security. As a member of the heterogeneous system design group of INL (Lyon Institute of nanotechnologies), he studies the integration and design of computing architectures based both on CMOS and emerging technologies such as ferroelectric FET, vertical nanowire transistors or silicon photonic. However, he keeps a particular interest in hardware security, from elementary logic gates to computing architecture design. His research is now focused on the impact of the integration of emerging technologies on the security of computing systems.