ZUCKERMAN Stéphane
Member of team :
CELL
Phone :
+33 1 30 73 62 69
+33 1 34 25 69 26
Biography
Stéphane Zuckerman graduated with a Ph.D in Computer Science from the University of Versailles, France in 2010, where he studied the emerging multicore systems and the behavior of high-performance applications on their memory subsystem.
From July 2010 to July 2016, S.Zuckerman worked at the Computer Architecture & Parallel Systems Laboratory at the University of Delaware, where, as a Research Associate, he helped specify the Codelet Model, a novel execution model for future extreme-scale supercomputers. He helped design and implement a runtime system which implements the Codelet Model, and also worked on of self-aware systems for power & energy-efficient high-performance computing.
After a year spent at the Michigan Technological University in 2016-2017 as a Visiting Professor, Dr. Zuckerman joined CY Cergy Paris Université, and the ETIS laboratory in the CELL team to work on parallel heterogeneous reconfigurable embedded systems.
Research activities
- Program execution models & parallel computing
- Reconfigurable & heterogeneous architectures
- IoT computing
- Resource management and task scheduling
Ongoing projects
- Autonomous vehicles localization: based on a bio-inspired algorithm researched by our colleagues in the Neurocybernetics team (N.Cuperlier, S.Colomer, and previously Y.Espada), we are working on porting that algorithm to a heterogeneous architecture comprised of a hybrid system-on-chip, with a 2-core ARM processor and a high-end FPGA. The end-result should be a system which is 20-50 times faster than its software counterpart, and consumes ~200 times less in power/energy. I help advise Tarek Elouaret, who is a student working for both CY and the VEDECOM consortium, which gathers important industrial actors (including major vehicle manufacturers) to perform some of the research as a common effort. The target is Wizarde, a custom multi-system-on-chip platform which gathers a 2D mesh of 9 (3×3) Zynq SoCs (i.e., dual-core ARM processors + 1 high-end FPGA).
- Exploiting connected objects to perform large-scale computations with low-power consumption: this project is only starting, but attempts to develop a methodology and a middleware to efficiently use idle objects in an IoT network rather than offload the work to a distant cloud-based system. The goal is to make computation as local as possible, and in particular to keep the produced data local as long as possible.
- Implementation of a distributed bio-inspired neural architecture on FPGA
- NoC-based hardware software co-design framework for dataflow thread management
- Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform
- A Profile-Based AI-Assisted Dynamic Scheduling Approach for Heterogeneous Architectures
